The trigger processor has removed the finder packets into the debug stream and replaced them with a timestamp for the scintillator trigger
The TP is fed the same 40 MHz clock of the MMFE8 boards to align the BC counter of the TP with the BC counter of the MMFE8/GBT packets in the ADDC
We have a inverter + TTL-to-LVDS converter for the scintillator signal, clock (clock doesn’t have an inverter)
16-bit timestamp (12 bit BCID, 4 bits of phase), 16-bits of “overflow”
data outputted is 64 bits: first 32 bits include header + scint counter, second 32 bits include overflow and timestamp
Layout
TTL-to-LVDS box is placed next to the trigger processor development board
The timing of the scintillator signal was switched to be set by the middle scintillator + PMT array (on top of the octuplet) so that the timing would be good to order ~ns
The scintillator signal is then clocked in by a 640 MHz clock in the TP FPGA to maintain the best
time resolution possible
Installed on May 10, 2017
tested with 1000 scint triggers, recorded 1000 scint triggers
Purpose
We want to understand if we can get a absolute timing ID from the MMTP (i.e. avg of the ART hits, first ART hit time, etc.)
To do this we need an absolute time for the muon event, which comes from the scintillator
Offline analysis of the time differences in the BC stamp of the ART hits and the 16-bit timestamp of the scintillator signal will evaluate the feasibility of this
